Semiconductor memories store digitally encoded data for personal computer systems, embedded processor-based systems, video imaging circuits, communication devices, and the like.
Typically, memory devices include an array of memory cells arranged in a series of columns and rows, wherein each memory cell includes a data storage element that stores at least one bit of data (e.g., a logical “1” or a logical “0”). Although these data storage elements provide generally reliable data retention, data errors can occur in some situations. Such a data error, for example, can cause a logical “1” that was expected to have been written to a cell to be read as a logical “0”, or vice versa. Because data errors can lead to undesirable consequences in the system, engineers strive to limit the number of data errors in memory devices.
Built-in-self-test (BIST) modules are one technology that has been developed to limit or prevent data errors. BIST modules typically write a pattern of “1”s and/or “0”s into the array, and then subsequently read the memory cells of the array to check whether the same pattern of “1”s and/or “0”s are read back. Often BIST testing is carried out before the memory devices are shipped to end customers (e.g., BIST testing is carried out in a fabrication facility), however, BIST testing can also be performed from time to time after customers have used the devices. In either case, if a faulty cell is identified, the BIST module can map the address of the faulty cell to that of a redundant (reliable) memory cell, such that memory operations intended to access the faulty cell are, unbeknownst to the end user, re-routed to the redundant (reliable) cell. This helps to ensure the end user receives a reliable memory device that accurately stores data.
Although conventional BIST methods are useful, the inventors have appreciated that more detailed information about the reliability of the memory cells of the array would be beneficial in many instances. For example, the inventors have appreciated that it would be helpful to generate data about read and/or write margins for the memory cells to help ward off future data errors due to “weak” memory cells. Accordingly, aspects of the present disclosure provide for techniques for verifying the reliability of memory cells.